In communication systems comprising apparatus for receiving an incoming synchronous serial binary data signal, it is advantageous to generate a periodic clock signal comprising pulses having a fixed phase relationship with pulses of the incoming data signal. To achieve a precise phase relationship, the clock signal may be derived from the data signal by utilization of a phase locked loop circuit. The theory and structure of both analog and digital phase locked loop circuits are well known in the art. Two references describing the general theory of phase locked loop circuits are Phase-Locked Loops, Alain Blanchard (John Wiley and Sons, 1976), and Phaselock Techniques, Floyd M. Gardner (John Wiley and Sons, 1966).
Several schemes exist within the prior art which utilize digital phase locked loop circuits for deriving a clock signal from an incoming data signal. One prior art disclosure in U.S. Pat. No. 3,714,589, R. Lewis, involving the use of a digital phase locked loop circuit to provide a closed loop system for generating a square-wave output signal shifted in time by a known, but variable amount from an input signal of the same frequency. The square-wave output signal is generated by utilizing a divider circuit and a variable counter circuit to adjust the phase of an output signal of a voltage controlled oscillator. The arrangement is limited to applications having a periodic data input signal, and is not adaptable for phase synchronization with an aperiodic data input signal.
A further prior art arrangement disclosed in U.S. Pat. No. 3,599,110, A. Gindi, utilizes a phase detection circuit comprising a plurality of pulse generators and timing circuitry for generating signals representative of frequency and phase errors between a data input signal and a clock signal. The arrangement provides means for synchronizing the phase and frequency of the clock signal to the data input signal. However, in the absence of a data signal pulse, representative of a binary zero, an error correction signal will be generated which always forces a voltage controlled oscillator to modify the frequency of its output signal in a specific direction. Such modification may force the clock signal to an erroneous frequency, or may cause overcorrection of the clock signal frequency.
U.S. Pat. No. 3,544,907, W. Bleickardt, describes an apparatus for generating timing pulses in synchronism with an incoming data signal. However, the apparatus described in the Bleickardt patent comprises complex signal differentiation and rectification circuitry for generating signals which may be transformed into pulses of equal periodicity through a monostable circuit means. A further limitation of prior art phase locked loop circuits is phase lock instability when the phase error between the clock signal and pulses of the incoming data signal is greater than a certain phase error. For an aperiodic data input signal, the phase lock instability may exist for a substantial period of time.